1. Field
Exemplary embodiments of the present invention relate to semiconductor device, and more particularly, to a duty rate detection circuit and a semiconductor device using the same.
2. Description of the Related Art
Semiconductor devices including a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) receive various signals from an external controller and perform diverse operations. Among the signals received from the external controller is a clock signal. A semiconductor device uses the clock signal as a source and generates an internal clock signal based on the clock signal. Since the semiconductor device performs an operation based on the internal clock signal, the frequency of the internal clock signal becomes the operation frequency of the semiconductor device. Therefore, the operation rate of the semiconductor device may be increased only by increasing the frequency of the internal clock signal. However, since there is limitation in raising the frequency of the internal clock signal, many methods for increasing the operation rate of a semiconductor device with a fixed frequency have been suggested. Among the methods is a method of increasing the applicability of a clock signal.
Conventional Single Data Rate (SDR) scheme is a method of outputting a data to a rising edge of a clock signal, and conventional Double Data Rate (DDR) scheme is a method of outputting a data to a rising edge and a falling edge of a clock signal. In other words, according to the DDR scheme, two data are outputted in one cycle of a clock signal. Therefore, when a semiconductor device with the DDR scheme and a semiconductor device with the SDR scheme receive clock signals of the same frequency, the semiconductor device with the DDR scheme may process twice as much data as the semiconductor device of the SDR scheme does. This signifies that the operation rate of the semiconductor device with the DDR scheme is twice as fast as that of the semiconductor device with the SDR scheme.
Meanwhile, since the DDR scheme uses the rising edge and falling edge of a clock signal, it is important to maintain the duty rate of the clock signal at 50:50. In other words, the logic high duration and the logic low duration of the clock signal have to be the same. If the duty rate of the clock signal goes out of 50:50 due to jitter and/or other reasons, data outputted in response to the clock signal may not be reliable. Thus, a circuit for controlling the duty rate of the clock signal is needed, and the circuit is called a duty rate correction circuit.
Meanwhile, the operation rate of semiconductor devices is getting faster and faster to satisfy users' demand. Faster operation rate means increasing frequency of the clock signal, which also means that it becomes more difficult to control the duty rate of the clock signal. Therefore, the industry and researchers are trying to delicately design the duty rate correction circuit.
FIG. 1 is a block diagram illustrating a conventional duty rate correction circuit.
Referring to FIG. 1, the duty rate correction circuit includes a duty rate correction block 110, a clock dividing block 120, a duty rate detection block 130 and a duty rate control block 140.
The duty rate correction block 110 is fed back with a duty control signal CTR, corrects the duty rate of an input clock signal CLK_IN and outputs a clock signal CLK_OUT with a corrected duty rate. The corrected clock signal CLK_OUT which is outputted from the duty rate correction block 110, has almost the same duty rate as that of the input clock signal CLK_IN that may not have a duty rate of 50:50 before a duty rate correction operation is performed, and, after the duty rate correction operation is performed, the corrected clock signal CLK_OUT has a duty rate of 50:50.
The clock dividing block divides the corrected clock signal CLK_OUT into a rising clock signal RCLK that corresponds to a rising edge and a falling dock signal FCLK that corresponds to a falling edge. The rising clock signal RCLK represents a logic high duration of the corrected clock signal CLK_OUT, and the falling clock signal FCLK represents a logic low duration of the corrected clock signal CLK_OUT. This will be described again later with reference to FIG. 3.
The duty rate detection block 130 detects a duty rate of the rising clock signal RCLK and the falling clock signal FCLK, which is the duty rate of the corrected clock signal CLK_OUT and generates a duty rate detection signal DET. The duty rate detection signal DET has a logic level value corresponding to the duty rate of the corrected clock signal CLK_OUT. For example, when the logic high duration of the corrected clock signal CLK_OUT is longer than the logic low duration, the duty rate detection signal DET may have a logic high value. When the logic low duration of the corrected clock signal CLK_OUT is longer than the logic high duration, the duty rate detection signal DET may have a logic low value.
The duty rate control block 140 generates the control signal CTR for controlling the duty rate of the input clock signal CLK_IN in response to the duty rate detection signal DET. The control signal CTR is fed back into the duty rate correction block 110, which controls the logic high duration or logic low duration of the input clock signal CLK_IN based on the control signal CTR and outputs the corrected clock signal CLK_OUT. The corrected dock signal CLK_OUT, which is generated through the above-described duty rate correction operation, has a duty rate of 50:50.
FIG. 2 is a circuit diagram illustrating the duty rate detection block 130 shown in FIG. 1.
Referring to FIG. 2, the duty rate detection block 130 includes a sense amplifier 210.
The sense amplifier 210 may include a cross-couple-type sense amplification circuit, and it receives the rising clock signal RCLK and the falling clock signal FCLK to generate a first output signal OUT1 and a second output signal OUT2. The sense amplifier 210 receives a strobe signal STB, and it controls starts of a charge operation and a discharge operation in response to the strobe signal STB. Although not illustrated in the drawing, the duty rate detection signal DET shown in FIG. 1 is generated in response to the first output signal OUT1 and the second output signal OUT2
FIG. 3 is a timing diagram illustrating operation of the sense amplifier 210 shown in FIG. 2. For clear description, it is assumed that the clock signal CLK_OUT is not fully corrected yet, and thus the logic high duration of the clock signal CLK_OUT is currently longer than the logic low duration. In short, the logic high duration of the rising clock signal RCLK is longer than the logic high duration of the falling clock signal FCLK.
Hereafter, the operation of the duty rate detection block 130 shown in FIG. 1 is described with reference to FIGS. 2 and 3.
The strobe signal STB is enabled and before a duty rate correction operation output are the first output signal OUT1 and the second output signal OUT2, which are pre-charged with a predetermined voltage through a charge operation. When the strobe signal STB is disabled, the first output signal OUT1 is gradually discharged while still in the logic high duration of the rising clock signal RCLK, and the second output signal OUT2 is gradually discharged while still in the logic high duration of the falling clock signal FCLK. After the discharge of the first output signal OUT1 and the second output signal OUT2 to some extent, when the difference between the voltage level of the first output signal OUT1 and the voltage level of the second output signal OUT2 becomes greater than a predetermined value, the first output signal OUT1 and the second output signal OUT2 are amplified to predetermined voltage levels, respectively. Since the logic high duration of the rising clock signal RCLK is longer than the logic high duration of the falling clock signal FCLK in this example, the first output signal OUT1 is pull-down amplified and the second output signal OUT2 is pull-up amplified.
The duty rate detection block 130 has the following drawbacks.
As shown in FIG. 3, after the discharge of the first output signal OUT1 and the second output signal OUT2 to some extent, when the voltage level difference between the first output signal OUT1 and the second output signal OUT2 becomes greater than the predetermined value, the first output signal OUT1 and the second output signal OUT2 are respectively amplified to the predetermined voltage levels. In this process, the numbers of the discharges of the first output signal OUT1 and of the second output signal OUT2 may be different. In other words, the first output signal OUT1 may be discharged seven times while the second output signal OUT2 may be discharged six times. After all, the amplification operation may be affected by the difference in the numbers of the discharges of the first output signal OUT1 and of the second output signal OUT2. This means that the first output signal OUT1 and the second output signal OUT2 are not reliably compared, and thus means that the duty rate of the corrected clock signal CLK_OUT may not be accurately detected.